Research Interests

• power management IC （high frequency DC-DC converters, 3-level buck converters and power amplifier supply modulators design.）
• analog IC

Personal Profile

Dr. Xun Liu is an assistant professor with the School of Science and Engineering (SSE), Chinese University of Hong Kong, Shenzhen. Her research interests include power management integrated circuits design, radio-frequency power amplifier system design for 5G, power management module design for Internet-of-Things (IoT), a monolithic system design of GaN device and its driver, etc.

Dr. Liu received the B.Eng. degree in Electronic and Information Engineering from Zhejiang University, China in 2011, and the Ph.D. degree in electronic and computer engineering from The Hong Kong University of Science and Technology (HKUST), Hong Kong, in 2017. She was a senior design engineer with Qualcomm, Santa Clara, CA, USA, working on cutting-edge integrated circuits and systems designs for 5G application and holding 2 US patents.

Dr. Liu is a technical program committee (TPC) member of International Solid-State Circuit Conference (ISSCC), the most prominent conference in the entire IC field. She published more than ten papers in IEEE journals and conferences in IC design. Her first-authored papers include one in ISSCC and 2 in Journal of Solid-State Circuits (JSSC), the most renowned journal in IC field.

Research

1、High-Frequency Three-Level Buck Converter for Average Power Tracking (APT) Systems

• The Three-Level Buck achieves a wider output range and higher efficiency.
• Operating at a high frequency with an equivalent doubling of the switching frequency (100MHz) to obtain a larger bandwidth, thereby achieving faster dynamic response.
• Real-time calibration circuitry ensures the reliability and various performance aspects of the chip.
• This chip is fabricated using the 65nm CMOS process.
• Published in top integrated circuit conferences, VLSI and the top integrated circuit journal, IEEE JSSC.

2、Novel Envelope Tracking (ET) System

• Envelop Tracking System Challenging requirements: Bandwidth: ~100MHz, Output Voltage Range: 0.5V ~ 2.5V, efficiency > 85%.
• The Power Amplifier (PA) employs CMOS integration, reducing costs, though at the expense of PA efficiency.

• Innovatively proposed Envelope-Shaping-and-Tracking technology to enhance the efficiency of both the PA and its power supply module.
• AC-coupling supply modulator composed of a 3-level switching amplifier and a wide bandwidth linear amplifier,broaden bandwidth,improve efficiency and response.
• Real-time calibration circuitry ensures the chip's reliability and various performance aspects.
• Performance complies with LTE standards and is more energy-efficient than other CMOS PA systems.
• Published in top integrated circuit conferences ISSCC and the top integrated circuit journal IEEE JSSC.

3、Wide-Voltage-Range and Fast-Transient Dual-CF Buck-or-Boost Converter

• The proposed dual-CF buck-or-boost converter can provide sub1V – 6V outputs covering Li-ion battery input voltage levels 2.7 – 4.2V.
• Operating at normal switching frequency 2MHz with peak efficiency up to 97.3% in the steady states and only below 6μs recovery time is needed during load transient response.
• Reference tacking enhancement techniques are applied to support approximately 1-2.5 μs/V dynamic voltage scaling rates.
• The chip is fabricated in 180nm BCD process with 1.8V, 5V CMOS and 6V LDMOS devices. Published in IEEE International Solid-State Circuits Conference (ISSCC).

4、High-Frequecny Multiphase Integrated Voltage Regulator(IVR) with in-package inductors

• The proposed IVR achieves a peak current density of 7A/mm2 and maximum output power of 8.4W.
• Operating at high switching frequency of 50MHz with 4-phase interleaving to utilize small power inductors and output capacitors, and obtain larger bandwidth for faster transient repsonse.
• Multiple-trigger-enabled transient enhancement technique is proposed for droop mitigation under extreme load transients.
• Ramp-level-adjusted current balance loop ensures robust multiphase operation at a high switching frequency.
• The chip is fabricated in a 28nm CMOS process and packaged in a Flip-Chip Chip Scale Package(FCCSP). Published in IEEE Asian Solid-State Circuits Conference (ASSCC).

Academic Services

• Program Committee Members

  • IEEE Int. Solid-State Circuits Conference (ISSCC), Power Subcommittee, 2021-current
  • International Workshop on Power Supply on Chip (PwrSoC), Committee, 2023-current
  • IEEE Int. Conference on Integrated Circuits, Technologies and Applications (ICTA), 2018.

• Government Committee Members

  • Shenzhen Science and Technology Innovation Committee Display Expert

• Conference Organizations

  • International Solid-State Circuits Conference (ISSCC) 2023 Session Chair
  • International Solid-State Circuits Conference (ISSCC) 2022 Session Chair
  • IEEE International Symposium on Circuits and Systems 2022 Session Chair
  • IEEE Asia Pacific Conference on Circuits and Systems 2022 Session Chair
  • Workshop on IC Advances in China (ICAC) 2021&2022 Session Chair